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ds07-12534-3e fujitsu semiconductor data sheet 8-bit proprietary microcontroller cmos f 2 mc-8l mb89620r series mb89623r/625r/p625/w625/626r/627r/p627/w627/t627r mb89pv620 n description the mb89620r series has been developed as a general-purpose version of the f 2 mc*-8l family consisting of proprietary 8-bit, single-chip microcontrollers. in addition to the f 2 mc-8l cpu core which can operate at low voltage but at high speed, the microcontrollers contain a variety of peripheral functions such as timers, serial interfaces, an a/d converter, and an external interrupt. the mb89620r series is applicable to a wide range of applications from consumer products to industrial equipment, including portable devices. *: f 2 mc stands for fujitsu flexible microcontroller. n features various package options three types of qfp packages (1 mm, 0.65 mm, or 0.5 mm lead pitch) sdip packages high-speed processing at low voltage minimum execution time: 0.4 m s/3.5 v, 0.8 m s/2.7 v ? 2 mc-8l family cpu core four types of timers 8-bit pwm timer (also usable as a reload timer) 8-bit pulse width count timer (continuous measurement capable, applicable to remote control, etc.) 16-bit timer/counter 20-bit timebase timer two serial interfaces switchable transfer direction allows communication with various equipment. 8-bit a/d converter sense mode function enabling comparison at 5 m s activation by an external input capable (continued) multiplication and division instructions 16-bit arithmetic operations test and branch instructions bit manipulation instructions, etc. instruction set optimized for controllers
2 mb89620r series (continued) external interrupt: 4 channels four channels are independent and capable of wake-up from low-power consumption modes (with an edge detection function). low-power consumption modes stop mode (oscillation stops to minimize the current cunsumption.) sleep mode (the cpu stops to reduce the current consumption to approx. 1/3 of normal.) bus interface functions including hold and ready functions n package 64-pin plastic sh-dip 64-pin plastic qfp 64-pin plastic qfp (dip-64p-m01) (fpt-64p-m06) (fpt-64p-m09) (dip-64c-a06) (mdp-64c-p02) (mqp-64c-p01) 64-pin plastic lqfp (fpt-64p-m03) 64-pin ceramic mdip 64-pin ceramic mqfp 64-pin ceramic sh-dip
3 mb89620r series n product lineup (continued) mb89623r mb89625r mb89626r mb89627r mb89t627r mb89p625 mb89w625 mb89p627 mb89w627 classi?ation mass production products (mask rom products) external rom products one-time prom products/eprom products piggyback/ evaluation product for evaluation and development rom size 8 k 8 bits (internal mask rom) 16 k 8 bits (internal mask rom) 24 k 8 bits (internal mask rom) 32 k 8 bits (internal mask rom) external rom 16 k 8 bits (internal prom, programmable with general- purpose eprom programmer) 32 k 8 bits (internal prom, programmable with general- purpose eprom programmer) 32 k 8 bits (external rom) ram size 256 8 bits 512 8 bits 768 8 bits 1 k 8 bits 1 k 8 bits 512 8 bits 1 k 8 bits 1 k 8 bits cpu functions number of instructions: 136 instruction bit length: 8 bits instruction length: 1 to 3 bytes data bit length: 1, 8, 16 bits minimum execution time: 0.4 m s /10 mhz interrupt processing time: 3.6 m s/10 mhz ports input ports: 5 (4 ports also serve as peripherals.) output ports (n-ch open-drain): 8 (all also serve as peripherals.) i/o ports (n-ch open-drain) 8 (4 ports also serve as peripherals.) output ports (cmos): 8 (all also serve as bus control pins.) i/o ports (cmos): 24 (all also serve as bus pins or peripherals.) total: 53 8-bit pwm timer 8-bit reload timer operation (toggled output capable, operating clock cycle: 0.4 m s to 3.3 ms) 8-bit resolution pwm operation (conversion cycle: 102 m s to 839 ms) 8-bit pulse width count timer 8-bit timer operation (overflow output capable, operating clock cycle: 0.4 to 12.8 m s) 8-bit reload timer operation (toggled output capable, operating clock cycle: 0.4 to 12.8 m s) 8-bit pulse width measurement operation (continuous measurement ??pulse width/??pulse width/from - to - /from to capable) 16-bit t imer/ counter 16-bit timer operation (operating clock cycle: 0.4 m s) 16-bit event counter operation (rising/falling/both edges selectable) 8-bit serial i/ o 1, 8-bit serial i/ o 2 8 bits lsb first/msb first selectable one clock selectable from four transfer clocks (one external shift clock, three internal shift clocks: 0.8 m s, 3.2 m s, 12.8 m s) 8-bit a/d converter 8-bit resolution 8 channels a/d conversion mode (conversion time: 18 m s) sense mode (conversion time: 5 m s) continuous activation by an external activation or an internal timer capable reference voltage input mb89pv620 part number parameter
4 mb89620r series (continued) *: varies with conditions such as the operating frequency. (see section n electrical characteristics.? n package and corresponding products : available : not available *: lead pitch converter sockets (manufacturer: sun hayato co., ltd.) are available. 64sd-64qf2-8l: for conversion from dip-64p-m01 or dip-64c-a06 to fpt-64p-m03 64sd-64sqf-8l: for conversion from dip-64p-m01 or dip-64c-a06 to fpt-64p-m09 inquiry: sun hayato co., ltd. : tel (81)-3-3986-0403 fax (81)-3-5396-9106 note: for more information about each package, see section n package dimensions. mb89623r mb89625r mb89626r mb89627r mb89t627r mb89p625 mb89w625 mb89p627 mb89w627 external interrupt 4 independent channels (edge selection, interrupt vector, source flag) rising edge/falling edge selectable used also for wake-up from stop/sleep mode. (edge detection is also permitted in stop mode.) standby modes sleep mode, stop mode process cmos operating voltage* 2.2 v to 6.0 v 2.7 v to 6.0 v eprom for use mbm27c256a-20tv mbm27c256a-20cz package mb89623r mb89625r mb89626r mb89627r mb89t627r mb89p625 mb89p627 mb89w625 mb89w627 mb89pv620 dip-64p-m01 fpt-64p-m03 * * * * fpt-64p-m06 fpt-64p-m09 * * * dip-64c-a06 mqp-64c-p01 mdp-64c-p02 mb89pv620 part number parameter
5 mb89620r series n differences among products 1. memory size before evaluating using the piggyback product, verify its differences from the product that will actually be used. take particular care on the following points: on the mb89623r, the upper half of the register bank cannot be used. on the mb89p627, the program area starts from address 8007 h but on the mb89pv620 and mb89627r starts from 8000 h . (on the mb89p627, addresses 8000 h to 8006 h comprise the option setting area, option settings can be read by reading these addresses. on the mb89pv620 and mb89627r, addresses 8000 h to 8006 h could also be used as a program rom. however, do not use these addresses in order to maintain compatibility of the mb89p627.) the stack area, etc., is set at the upper limit of the ram. the external area is used. 2. current consumption in the case of the mb89pv620, add the current consumed by the eprom which is connected to the top socket. when operated at low speed, the product with an otprom (one-time prom) or an eprom will consume more current than the product with a mask rom. however, the current consumption in sleep/stop modes is the same. (for more information, see section n electrical characteristics?) 3. mask options functions that can be selected as options and how to designate these options vary by the product. before using options check section n mask options. take particular care on the following points: a pull-up resistor cannot be set for p40 to p47 on the mb89p625, mb89w625, mb89p627, and mb89w627. a pull-up resistor is not selectable for p50 to p57 when the a/d converter is used. options are ?ed on the mb89pv620.
6 mb89620r series 4. differences between the mb89620 and mb89620r series memory access area memory access area of the following products is the same; both the mb89625 and mb89625r, and both the mb89627 and mb89627r. the access area of the mb89623 and mb89626 is different from that of the mb89623r and mb89626r respectively when using in external bus mode. see below. other speci?ations both the mb89620r and mb89620 series is the same. electrical speci?ations/electrical characteristics electrical speci?ations of the mb89620r series are the same with that of the mb89620 series. n correspondence between the mb89620 and mb89620r series the mb89620r series is the reduction version of the mb89620 series. the mb89620 and mb89620r series consist of the following products: address memory area mb89623 mb89623r 0000 h to 007f h i/o area i/o area 0080 h to 017f h ram area ram area 0180 h to 027f h external area access prohibited 0280 h to bfff h external area c000 h to dfff h access prohibited e000 h to ffff h rom area rom area address memory area mb89626 mb89626r 0000 h to 007f h i/o area i/o area 0080 h to 037f h ram area ram area 0380 h to 047f h external area access prohibited 0480 h to 7fff h external area 8000 h to 9fff h access prohibited a000 h to ffff h rom area rom area mb89620 series mb89623 mb89625 mb89626 mb896267 mb89p625 mb89p627 mb89pv620 mb89620r series mb89623r mb89625r mb89626r mb896267 r mb89620 series mb89w625 mb89w627 mb89t627r mb89620r series
7 mb89620r series n pin assignment (dip-64p-m01) (top view) (dip-64c-a06) (mdp-64c-p02) 65 v pp 66 a12 67 a7 68 a6 69 a5 70 a4 71 a3 72 a2 73 a1 74 a0 75 o1 76 o2 77 o3 78 v ss v cc 92 a14 91 a13 90 a8 89 a9 88 a11 87 oe 86 a10 85 ce 84 o8 83 o7 82 o6 81 o5 80 o4 79 1 p36/wto 2 p37/pto 3 p40 4 p41 5 p42 6 p43 7 p44/bz 8 p45/sck2 9 p46/so2 10 p47/si2 11 p50/an0 12 p51/an1 13 p52/an2 14 p53/an3 15 p54/an4 16 p55/an5 17 p56/an6 18 p57/an7 19 av cc 20 avr 21 av ss 22 p60/int0 23 p61/int1 24 p62/int2 25 p63/int3 26 p64 27 rst 28 mod0 29 mod1 30 x0 31 x1 32 v ss v cc 64 p35/pwc 63 p34/ec 62 p33/si1 61 p32/so1 60 p31/sck1 59 p30/adst 58 v ss 57 p00/ad0 56 p01/ad1 55 p02/ad2 54 p03/ad3 53 p04/ad4 52 p05/ad5 51 p06/ad6 50 p07/ad7 49 p10/a08 48 p11/a09 47 p12/a10 46 p13/a11 45 p14/a12 44 p15/a13 43 p16/a14 42 p17/a15 41 p20/bufc 40 p21/hak 39 p22/hrq 38 p23/rdy 37 p24/clk 36 p25/wr 35 p26/rd 34 p27/ale 33 each pin inside the dashed line is for the mb89pv620 only. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 p46/so2 p47/si2 p50/an0 p51/an1 p52/an2 p53/an3 p54/an4 p55/an5 p56/an6 p57/an7 av cc avr av ss p60/int0 p61/int1 p62/int2 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 p00/ad0 p01/ad1 p02/ad2 p03/ad3 p04/ad4 p05/ad5 p06/ad6 p07/ad7 p10/a08 p11/a09 p12/a10 p13/a11 p14/a12 p15/a13 p16/a14 p17/a15 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 p45/sck2 p44/bz p43 p42 p41 p40 p37/pto p36/wto v cc p35/pwc p34/ec p33/si1 p32/so1 p31/sck1 p30/adst v ss 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 p63/int3 p64 rst mod0 mod1 x0 x1 v ss p27/ale p26/rd p25/wr p24/clk p23/rdy p22/hrq p21/hak p20/bufc (fpt-64p-m03) (top view) (fpt-64p-m09)
8 mb89620r series pin assignment on package top (mb89pv620 only) n.c.: internally connected. do not use. pin no. pin name pin no. pin name pin no. pin name pin no. pin name 65 n.c. 73 a2 81 n.c. 89 oe 66 v pp 74 a1 82 o4 90 n.c. 67 a12 75 a0 83 o5 91 a11 68 a7 76 n.c. 84 o6 92 a9 69 a6 77 o1 85 o7 93 a8 70 a5 78 o2 86 o8 94 a13 71 a4 79 o3 87 ce 95 a14 72 a3 80 v ss 88 a10 96 v cc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 p45/sck2 p46/so2 p47/si2 p50/an0 p51/an1 p52/an2 p53/an3 p54/an4 p55/an5 p56/an6 p57/an7 av cc avr av ss p60/int0 p61/int1 p62/int2 p63/int3 p64 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 p30/adst v ss p00/ad0 p01/ad1 p02/ad2 p03/ad3 p04/ad4 p05/ad5 p06/ad6 p07/ad7 p10/a08 p11/a09 p12/a10 p13/a11 p14/a12 p15/a13 p16/a14 p17/a15 p20/bufc 64 63 62 61 60 59 58 57 56 55 54 53 52 p44/bz p43 p42 p41 p40 p37/pto p36/wto v cc p35/pwc p34/ec p33/si1 p32/so1 p31/sck1 20 21 22 23 24 25 26 27 28 29 30 31 32 rst mod0 mod1 x0 x1 v ss p27/ale p26/rd p25/wr p24/clk p23/rdy p22/hrq p21/hak 85 86 87 88 89 90 91 92 93 77 76 75 74 73 72 71 70 69 84 83 82 81 80 79 78 94 95 96 65 66 67 68 (top view) (fpt-64p-m06) (mqp-64c-p01) each pin inside the dashed line is for the mb89pv620 only.
9 mb89620r series n pin description (continued) *1: dip-64p-m01, dip-64c-a06 *2: mdp-64c-p02 *3: fpt-64p-m06 *4: mqp-64c-p01 *5: fpt-64p-m03 *6: fpt-64p-m09 pin no. pin name circuit type function sh-dip *1 mdip *2 qfp1 *3 mqfp *4 lqfp *5 qfp2 *6 30 23 22 x0 a crystal oscillator pins 31 24 23 x1 28 21 20 mod0 b operating mode selection pins connect directly to v cc or v ss . 29 22 21 mod1 27 20 19 rst c reset i/o pin this pin is an n-ch open-drain output type with a pull-up resistor, and a hysteresis input type. ? is output from this pin by an internal reset source. the internal circuit is initialized by the input of ?? 56 to 49 49 to 42 48 to 41 p00/ad0 to p07/ad7 d general-purpose i/o ports when an external bus is used, these ports function as multiplex pins of lower address output and data i/o. 48 to 41 41 to 34 40 to 33 p10/a08 to p17/a15 d general-purpose i/o ports when an external bus is used, these ports function as upper address output. 40 33 32 p20/bufc f general-purpose output-only port when an external bus is used, this port can also be used as a buffer control output by setting the bctr. 39 32 31 p21/hak f general-purpose output-only port when an external bus is used, this port can also be used as a hold acknowledge output by setting the bctr. 38 31 30 p22/hrq d general-purpose output-only port when an external bus is used, this port can also be used as a hold request input by setting the bctr. 37 30 29 p23/rdy d general-purpose output-only port when an external bus is used, this port functions as a ready input. 36 29 28 p24/clk f general-purpose output-only port when an external bus is used, this port functions as a clock output. 35 28 27 p25/wr f general-purpose output-only port when an external bus is used, this port functions as a write signal output. 34 27 26 p26/rd f general-purpose output-only port when an external bus is used, this port functions as a read signal output. 33 26 25 p27/ale f general-purpose output-only port when an external bus is used, this port functions as an address latch signal output.
10 mb89620r series (continued) (continued) *1: dip-64p-m01, dip-64c-a06 *2: mdp-64c-p02 *3: fpt-64p-m06 *4: mqp-64c-p01 *5: fpt-64p-m03 *6: fpt-64p-m09 pin no. pin name circuit type function sh-dip *1 mdip *2 qfp1 *3 mqfp *4 lqfp *5 qfp2 *6 58 51 50 p30/adst e general-purpose i/o port also serves as an a/d converter external activation. this port is a hysteresis input type. 59 52 51 p31/sck1 e general-purpose i/o port also serves as the clock i/o for the 8-bit serial i/o 1. this port is a hysteresis input type. 60 53 52 p32/so1 e general-purpose i/o port also serves as the data output for the 8-bit serial i/o 1. this port is a hysteresis input type. 61 54 53 p33/si1 e general-purpose i/o port also serves as the data input for the 8-bit serial i/o 1. this port is a hysteresis input type. 62 55 54 p34/ec e general-purpose i/o port also serves as the external clock input for the 16-bit timer/counter. this port is a hysteresis input type. 63 56 55 p35/pwc e general-purpose i/o port also serves as the measured pulse input for the 8-bit pulse width count timer. this port is a hysteresis input type. 1 58 57 p36/wto e general-purpose i/o port also serves as the toggle output for the 8-bit pulse width count timer. this port is a hysteresis input type. 2 59 58 p37/pto e general-purpose i/o port also serves as the toggle output for the 8-bit pwm timer. this port is a hysteresis input type. 3 to 6 60 to 63 59 to 62 p40 to p43 g n-ch open-drain i/o ports these ports are a hysteresis input type. 7 64 63 p44/bz g n-ch open-drain i/o port also serves as a buzzer output. this port is a hysteresis input type. 8 1 64 p45/sck2 g n-ch open-drain i/o port also serves as the clock i/o for the 8-bit serial i/o 2. this port is a hysteresis input type. 9 2 1 p46/so2 g n-ch open-drain i/o port also serves as the data output for the 8-bit serial i/o 2. this port is a hysteresis input type. 10 3 2 p47/si2 g n-ch open-drain i/o port also serves as the data input for the 8-bit serial i/o 2. this port is a hysteresis input type.
11 mb89620r series (continued) *1: dip-64p-m01, dip-64c-a06 *2: mdp-64c-p02 *3: fpt-64p-m06 *4: mqp-64c-p01 *5: fpt-64p-m03 *6: fpt-64p-m09 pin no. pin name circuit type function sh-dip *1 mdip *2 qfp1 *3 mqfp *4 lqfp *5 qfp2 *6 11 to 18 4 to 11 3 to 10 p50/an0 to p57/an7 h n-ch open-drain output-only ports also serve as the analog input for the a/d converter. 22 to 25 15 to 18 14 to 17 p60/int0 to p63/int3 i general-purpose input-only ports also serve as an external interrupt input. these ports are a hysteresis input type. 26 19 18 p64 i general-purpose input-only port this port is a hysteresis input type. 64 57 56 v cc power supply pin 32, 57 25, 50 24, 49 v ss power supply (gnd) pins 19 12 11 av cc a/d converter power supply pin 20 13 12 avr a/d converter reference voltage input pin 21 14 13 av ss a/d converter power supply (gnd) pin use this pin at the same voltage as v ss.
12 mb89620r series external eprom pins (mb89pv620 only) *1: mdp-64c-p02 *2: mqp-64c-p01 pin no. pin name i/o function mdip *1 mqfp *2 65 66 v pp o ? level output pin 66 67 68 69 70 71 72 73 74 67 68 69 70 71 72 73 74 75 a12 a7 a6 a5 a4 a3 a2 a1 a0 o address output pins 75 76 77 77 78 79 o1 o2 o3 i data input pins 78 80 v ss o power supply (gnd) pin 79 80 81 82 83 82 83 84 85 86 o4 o5 o6 o7 o8 i data input pins 84 87 ce o rom chip enable pin outputs ??during standby. 85 88 a10 o address output pin 86 89 oe o rom output enable pin outputs ??at all times. 87 88 89 91 92 93 a11 a9 a8 o address output pins 90 94 a13 o 91 95 a14 o 92 96 v cc o eprom power supply pin ?5 76 81 90 n.c. internally connected pins be sure to leave them open.
13 mb89620r series n i/o circuit type (continued) type circuit remarks a at an oscillation feedback resistor of approximately 1 m w /5.0 v b c at an output pull-up resistor (p-ch) of approximately 50 k w /5.0 v hysteresis input d cmos output cmos input pull-up resistor optional (except p22 and p23) e cmos output hysteresis input pull-up resistor optional f cmos output x1 x0 standby control signal r p-ch n-ch p-ch n-ch r p-ch n-ch r p-ch n-ch
14 mb89620r series (continued) type circuit remarks g n-ch open-drain output hysteresis input pull-up resistor optional (mb89623r, mb89625r, mb89626r, and mb89627r only) h n-ch open-drain output analog input pull-up resistor optional i hysteresis input pull-up resistor optional r n-ch analog input r n-ch r
15 mb89620r series n handling devices 1. preventing latchup latchup may occur on cmos ics if voltage higher than v cc or lower than v ss is applied to input and output pins other than medium- and high-voltage pins or if higher than the voltage which shows on ?. absolute maximum ratings in section n electrical characteristics is applied between v cc and v ss . when latchup occurs, power supply current increases rapidly and might thermally damage elements. when using, take great care not to exceed the absolute maximum ratings. also, take care to prevent the analog power supply (av cc and avr) and analog input from exceeding the digital power supply (v cc ) when the analog system power supply is turned on and off. 2. treatment of unused input pins leaving unused input pins open could cause malfunctions. they should be connected to a pull-up or pull-down resistor. 3. treatment of power supply pins on microcontrollers with a/d and d/a converters connect to be av cc = davc = v cc and av ss = avr = v ss even if the a/d and d/a converters are not in use. 4. treatment of n.c. pins be sure to leave (internally connected) n.c. pins open. 5. power supply voltage fluctuations although v cc power supply voltage is assured to operate within the rated range, a rapid ?ctuation of the voltage could cause malfunctions, even if it occurs within the rated range. stabilizing voltage supplied to the ic is therefore important. as stabilization guidelines, it is recommended to control power so that v cc ripple ?ctuations (p-p value) will be less than 10% of the standard v cc value at the commercial frequency (50 to 60 hz) and the transient ?ctuation rate will be less than 0.1 v/ms at the time of a momentary ?ctuation such as when power is switched. 6. precautions when using an external clock when an external clock is used, oscillation stabilization time is required even for power-on reset (optional) and wake-up from stop mode.
16 mb89620r series n programming to the eprom on the mb89p625 the mb89p625 is an otprom version of the mb89620r series. 1. features 16-kbyte prom on chip options can be set using the eprom programmer. equivalency to the mbm27c256a in eprom mode (when programmed with the eprom programmer) 2. memory space memory space in each mode such as 16-kbyte prom, option area is diagrammed below. 3. programming to the eprom in eprom mode, the mb89p625 functions equivalent to the mbm27c256a. this allows the prom to be programmed with a general-purpose eprom programmer (the electronic signature mode cannot be used) by using the dedicated socket adapter. when the operating rom area for a single chip is 16 kbytes (c000 h to ffff h ) the prom can be programmed as follows: programming procedure (1) set the eprom programmer to the mbm27c256a. (2) load program data into the eprom programmer at 4000 h to 7fff h (note that addresses c000 h to ffff h while operating as a single chip assign to 4000 h to 7fff h in eprom mode). load option data into addresses 3ff0 h to 3ff5 h of the eprom programmer. (for information about each corresponding option, see ?. setting otprom options.? (3) program to 3ff0 h to 7fff h with the eprom programmer. i/o ram external area external area external area prom 16 kb eprom 16 kb vacancy (read value: ff h ) option area 0000 h 0080 h 0280 h bff0 h bff6 h c000 h ffff h 3ff0 h 3ff6 h 4000 h 7fff h address single chip eprom mode (corresponding addresses on the eprom programmer)
17 mb89620r series 4. setting otprom options the programming procedure is the same as that for the prom. options can be set by programming values at the addresses shown on the memory map. the relationship between bits and options is shown on the following bit map: otprom option bit map (mb89p625) note: each bit is set to ? as the initialized value, therefore the pull-up option is not selected. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 3ff0 h vacancy readable and writable vacancy readable and writable vacancy readable and writable vacancy readable and writable vacancy readable and writable reset pin output 1: yes 0: no oscillation stabilizatio ntime 1: crystal 0: ceramic power-on reset 1: yes 0: no 3ff1 h p07 pull-up 1: no 0: yes p06 pull-up 1: no 0: yes p05 pull-up 1: no 0: yes p04 pull-up 1: no 0: yes p03 pull-up 1: no 0: yes p02 pull-up 1: no 0: yes p01 pull-up 1: no 0: yes p00 pull-up 1: no 0: yes 3ff2 h p17 pull-up 1: no 0: yes p16 pull-up 1: no 0: yes p15 pull-up 1: no 0: yes p14 pull-up 1: no 0: yes p13 pull-up 1: no 0: yes p12 pull-up 1: no 0: yes p11 pull-up 1: no 0: yes p10 pull-up 1: no 0: yes 3ff3 h p37 pull-up 1: no 0: yes p36 pull-up 1: no 0: yes p35 pull-up 1: no 0: yes p34 pull-up 1: no 0: yes p33 pull-up 1: no 0: yes p32 pull-up 1: no 0: yes p31 pull-up 1: no 0: yes p30 pull-up 1: no 0: yes 3ff4 h p57 pull-up 1: no 0: yes p56 pull-up 1: no 0: yes p55 pull-up 1: no 0: yes p54 pull-up 1: no 0: yes p53 pull-up 1: no 0: yes p52 pull-up 1: no 0: yes p51 pull-up 1: no 0: yes p50 pull-up 1: no 0: yes 3ff5 h vacancy readable and writable vacancy readable and writable vacancy readable and writable p64 pull-up 1: no 0: yes p63 pull-up 1: no 0: yes p62 pull-up 1: no 0: yes p61 pull-up 1: no 0: yes p60 pull-up 1: no 0: yes
18 mb89620r series n programming to the eprom on the mb89p627 the mb89p627 is an otprom version of the mb89620r series. 1. features 32-kbyte prom on chip options can be set using the eprom programmer. equivalency to the mbm27c256a in eprom mode (when programmed with the eprom programmer) 2. memory space memory space in each mode such as 32-kbyte prom, option area is diagrammed below. 3. programming to the eprom in eprom mode, the mb89p627 functions equivalent to the mbm27c256a. this allows the prom to be programmed with a general-purpose eprom programmer (the electronic signature mode cannot be used) by using the dedicated socket adapter. when the operating rom area for a single chip is 32 kbytes (8007 h to ffff h ) the prom can be programmed as follows: programming procedure (1) set the eprom programmer to the mbm27c256a. (2) load program data into the eprom programmer at 0007 h to 7fff h (note that addresses 8007 h to ffff h while operating as a single chip assign to 0007 h to 7fff h in eprom mode). load option data into addresses 0000 h to 0006 h of the eprom programmer. (for information about each corresponding option, see ?. setting otprom options.? (3) program to 0000 h to 7fff h with the eprom programmer. i/o ram external area external area prom 32 kb eprom 32 kb option area 0000 h 0080 h 0480 h 8000 h 8007 h ffff h 0000 h 0007 h 7fff h address single chip eprom mode (corresponding addresses on the eprom programmer)
19 mb89620r series 4. setting otprom options the programming procedure is the same as that for the prom. options can be set by programming values at the addresses shown on the memory map. the relationship between bits and options is shown on the following bit map: otprom option bit map (mb89p627) note: each bit is set to ? as the initialized value, therefore the pull-up option is not selected. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0000 h vacancy readable and writable vacancy readable and writable vacancy readable and writable vacancy readable and writable vacancy readable and writable reset pin output 1: yes 0: no oscillation stabilizatio ntime 1: crystal 0: ceramic power-on reset 1: yes 0: no 0001 h p07 pull-up 1: no 0: yes p06 pull-up 1: no 0: yes p05 pull-up 1: no 0: yes p04 pull-up 1: no 0: yes p03 pull-up 1: no 0: yes p02 pull-up 1: no 0: yes p01 pull-up 1: no 0: yes p00 pull-up 1: no 0: yes 0002 h p17 pull-up 1: no 0: yes p16 pull-up 1: no 0: yes p15 pull-up 1: no 0: yes p14 pull-up 1: no 0: yes p13 pull-up 1: no 0: yes p12 pull-up 1: no 0: yes p11 pull-up 1: no 0: yes p10 pull-up 1: no 0: yes 0003 h p37 pull-up 1: no 0: yes p36 pull-up 1: no 0: yes p35 pull-up 1: no 0: yes p34 pull-up 1: no 0: yes p33 pull-up 1: no 0: yes p32 pull-up 1: no 0: yes p31 pull-up 1: no 0: yes p30 pull-up 1: no 0: yes 0004 h p57 pull-up 1: no 0: yes p56 pull-up 1: no 0: yes p55 pull-up 1: no 0: yes p54 pull-up 1: no 0: yes p53 pull-up 1: no 0: yes p52 pull-up 1: no 0: yes p51 pull-up 1: no 0: yes p50 pull-up 1: no 0: yes 0005 h vacancy readable and writable vacancy readable and writable vacancy readable and writable p64 pull-up 1: no 0: yes p63 pull-up 1: no 0: yes p62 pull-up 1: no 0: yes p61 pull-up 1: no 0: yes p60 pull-up 1: no 0: yes 0006 h vacancy readable and writable vacancy readable and writable vacancy readable and writable vacancy readable and writable vacancy readable and writable vacancy readable and writable vacancy readable and writable vacancy readable and writable
20 mb89620r series n handling the mb89p625/p627 1. recommended screening conditions high-temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked otprom microcomputer program. 2. programming yield all bits cannot be programmed at fujitsu shipping test to a blanked otprom microcomputer, due to its nature. for this reason, a programming yield of 100% cannot be assured at all times. 3. erasure in order to clear all locations of their programmed contents, it is necessary to expose the internal eprom to an ultraviolet light source. a dosage of 10 w-seconds/cm 2 is required to completely erase an internal eprom. this dosage can be obtained by exposure to an ultraviolet lamp (wavelength of 2537 angstroms (?)) with intensity of 12000 m w/cm 2 for 15 to 21 minutes. the internal eprom should be about one inch from the source and all ?ters should be removed from the uv light source prior to erasure. it is important to note that the internal eprom and similar devices, will erase with light sources having wavelengths shorter than 4000?. although erasure time will be much longer than with uv source at 2537?, nevertheless the exposure to ?orescent light and sunlight will eventually erase the internal eprom, and exposure to them should be prevented to realize maximum system reliability. if used in such an environment, the package windows should be covered by an opaque label or substance. aging +150 c, 48 hrs. data verification assembly program, verify
21 mb89620r series 4. eprom programmer socket adapter and recommended programmer manufacturer *: it is required to connect a capacitor of approximately 0.1 m f between v pp and gnd, and v cc and gnd . inquiry: sun hayato co., ltd. : tel (81)-3-3986-0403 fax (81)-3-5396-9106 minato electronics inc.: tel: usa (1)-916-348-6066 japan (81)-45-591-5611 data i/o co., ltd: tel: usa/asia (1)-206-881-6444 europe (49)-8-985-8580 advantest corp. :tel: except japan (81)-3-3930-4111 part number package compatible socket adapter sun hayato co., ltd. recommended programmer manufacturer and programmer name minato electronics inc. data i/o co., ltd. advantest corp. 1890a 1891 unisite 3900 2900 r4945a mb89p625p-sh sh-dip-64 rom-64sd-28dp-8l recommended recommended recommended mb89p625pf qfp-64 rom-64qf-28dp-8l recommended* recommended recommended mb89p625pfm qfp-64 rom-64qf2-28dp-8l recommended* recommended recommended
22 mb89620r series n programming to the eprom piggyback/evaluation device 1. eprom for use mbm27c256a-20tv, mbm27c256a-20cz 2. programming socket adapter to program to the prom using an eprom programmer, use the socket adapter (manufacturer: sun hayato co., ltd.) listed below. inquiry: sun hayato co., ltd.: tel (81)-3-3986-0403 fax (81)-3-5396-9106 3. memory space memory space in 32-kbyte prom is diagrammed below. 4. programming to the eprom (1) set the eprom programmer to the mbm27c256a. (2) load program data into the eprom programmer at 0006 h to 7fff h . (3) program to 0000 h to 7fff h with the eprom programmer. package adapter socket part number lcc-32 (rectangle) rom-32lc-28dp-yg i/o ram prom 32 kb 0000 h 0080 h 0480 h 8000 h 8006 h ffff h 0000 h 0006 h 7fff h address single chip corresponding addresses on the eprom programmer not available not available eprom 32 kb not available
23 mb89620r series n block diagram x0 x1 oscillator rst clock controller reset circuit (wdt) 8 8 p00/ad0 to p07/ad7 p10/a08 to p17/a15 cmos i/o port external bus interface mod0 mod1 p27/ale p26/rd p25/wr p24/clk p23/rdy p22/hrq p21/hak p20/bufc cmos output port f 2 mc-8l cpu rom v cc , v ss 2 the other pins 20-bit timebase timer 8-bit pwm timer 8-bit pulse width count timer 16-bit timer/counter 8-bit serial i/o 1 cmos i/o port buzzer output n-ch open-drain output port 8-bit a/d converter 4 4 external interrupt input port p60/int0 to p63/int3 8 p64 avr av cc av ss 8 p50/an0 to p57/an7 p40 to p43 p44/bz p45/sck2 p46/so2 p47/si2 p30/adst p31/sck1 p32/so1 p33/si1 p34/ec p35/pwc p36/wto p37/pto port 2 ports 0 and 1 8-bit serial i/o 2 n-ch open-drain i/o port port 4 port 5 port 6 port 3 ram 4 internal bus
24 mb89620r series n cpu core 1. memory space the microcontrollers of the mb89620r series offer a memory space of 64 kbytes for storing all of i/o, data, and program areas. the i/o area is located at the lowest address. the data area is provided immediately above the i/o area. the data area can be divided into register, stack, and direct areas according to the application. the program area is located at exactly the opposite end, that is, near the highest address. provide the tables of interrupt reset vectors and vector call instructions toward the highest address within the program area. the memory space of the mb89620r series is structured as illustrated below. memory space *1: the rom area is an external area depending on the mode. *2: since addresses 8000 h to 8005 h for the mb89p627 and mb89w627 comprise an option area, do not use this area for the mb89pv620 and mb89627r. *3: access to this area is prohibited when using external bus mode. 0000 h 0080 h 0100 h 0480 h 8000 h mb89pv620 i/o register external area 0000 h 0080 h 0100 h 0180 h c000 h e000 h ffff h mb89623r i/o 0000 h 0080 h 0100 h 0200 h c000 h ffff h ffff h ffff h mb89625r mb89p625 mb89w625 i/o 0000 h 0080 h 0100 h 0200 h mb89626r i/o 0000 h 0080 h 0100 h 0200 h mb89627r mb89p627 mb89t627r mb89w627 i/o ffff h 0280 h external area external area 0380 h 0280 h 0200 h 8000 h 8006 h external area 0480 h 8000 h a000 h external area 0480 h register register register register * 2 * 2 * 3 rom* 8 kb 1 ram 1 kb ram 256 b ram 512 b ram 768 b ram 1 kb external rom 32 kb rom* 16 kb 1 rom 24 kb rom 32 kb 8006 h * 3 * 3 * 3
25 mb89620r series 2. registers the f 2 mc-8l family has two types of registers; dedicated registers in the cpu and general-purpose registers in the memory. the following dedicated registers are provided: program counter (pc): a 16-bit register for indicating instruction storage positions accumulator (a): a 16-bit temporary register for storing arithmetic operations, etc. when the instruction is an 8-bit data processing instruction, the lower byte is used. temporary accumulator (t): a 16-bit register which performs arithmetic operations with the accumulator when the instruction is an 8-bit data processing instruction, the lower byte is used. index register (ix): a 16-bit register for index modi?ation extra pointer (ep): a 16-bit pointer for indicating a memory address stack pointer (sp): a 16-bit register for indicating a stack area program status (ps): a 16-bit register for storing a register pointer, a condition code the ps can further be divided into higher 8 bits for use as a register bank pointer (rp) and the lower 8 bits for use as a condition code register (ccr). (see the diagram below.) pc a t ix ep sp ps 16 bits : program counter : accumulator : temporary accumulator : index register : extra pointer : stack pointer : program status fffd h indeterminate indeterminate indeterminate indeterminate indeterminate i-flag = 0, il1, 0 = 11 the other bit values are indeterminate. initial value structure of the program status register vacancy h i il1, 0 n z vc 54 rp ps 109876 3210 15 14 13 12 11 rp ccr vacancy vacancy
26 mb89620r series the rp indicates the address of the register bank currently in use. the relationship between the pointer contents and the actual address is based on the conversion rule illustrated below. the ccr consists of bits indicating the results of arithmetic operations and the contents of transfer data and bits for control of cpu operations at the time of an interrupt. h-?g: set to ? when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. cleared to ? otherwise. this ?g is for decimal adjustment instructions. i-?g: interrupt is enabled when this ?g is set to ?? interrupt is disabled when the ?g is cleared to ?? cleared to ? at the reset. il1, 0: indicates the level of the interrupt currently allowed. processes an interrupt only if its request level is higher than the value indicated by this bit. n-?g: set to ? if the msb becomes ? as the result of an arithmetic operation. cleared to ? when the bit is cleared to ?? z-?g: set to ? when an arithmetic operation results in 0. cleared to ? otherwise. v-?g: set to ? if the complement on 2 over?ws as a result of an arithmetic operation. cleared to ? if the over?w does not occur. c-?g: set to ? when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. cleared to ? otherwise. set to the shift-out value in the case of a shift instruction. il1 il0 interrupt level high-low 00 1 high low 01 10 2 11 3 rule for conversion of actual addresses of the general-purpose register area ? a15 ? a14 ? a13 ? a12 ? a11 ? a10 ? a9 ? a8 r4 a7 r3 a6 r2 a5 r1 a4 r0 a3 b2 a2 b1 a1 b0 a0 lower op codes rp generated addresses
27 mb89620r series the following general-purpose registers are provided: general-purpose registers: an 8-bit register for storing data the general-purpose registers are 8 bits and located in the register banks of the memory. one bank contains eight registers and up to a total of 32 banks can be used on the mb89620r. in the mb89623r, there are 16 banks in internal ram. the remaining 16 banks can be extended externally by allocating an external ram to addresses 0180 h to 01ff h using an external circuit. the bank currently in use is indicated by the register bank pointer (rp). note: the number of register banks that can be used varies with the ram size. register bank configuration r 1 r 2 r 3 r 4 r 5 r 6 r 7 this address = 0100 h + 8 (rp) memory area 32 banks r 0
28 mb89620r series n i/o map (continued) address read/write register name register description 00 h (r/w) pdr0 port 0 data register 01 h (w) ddr0 port 0 data direction register 02 h (r/w) pdr1 port 1 data register 03 h (w) ddr1 port 1 data direction register 04 h (r/w) pdr2 port 2 data register 05 h (r/w) bctr external bus pin control register 06 h vacancy 07 h vacancy 08 h (r/w) stbc standby control register 09 h (r/w) wdtc watchdog timer control register 0a h (r/w) tbtc timebase timer control register 0b h vacancy 0c h (r/w) pdr3 port 3 data register 0d h (w) ddr3 port 3 data direction register 0e h (r/w) pdr4 port 4 data register 0f h (r/w) bzcr buzzer register 10 h (r/w) pdr5 port 5 data register 11 h (r) pdr6 port 6 data register 12 h (r/w) cntr pwm control register 13 h (w) comr pwm compare register 14 h (r/w) pcr1 pwc pulse width control register 1 15 h (r/w) pcr2 pwc pulse width control register 2 16 h (r/w) rlbr pwc reload buffer register 17 h vacancy 18 h (r/w) tmcr 16-bit timer control register 19 h (r/w) tchr 16-bit timer count register (h) 1a h (r/w) tclr 16-bit timer count register (l) 1b h vacancy 1c h (r/w) smr1 serial i/o 1 mode register 1d h (r/w) sdr1 serial i/o 1 data register 1e h (r/w) smr2 serial i/o 2 mode register 1f h (r/w) sdr2 serial i/o 2 data register
29 mb89620r series (continued) note: do not use vacancies. address read/write register name register description 20 h (r/w) adc1 a/d converter control register 1 21 h (r/w) adc2 a/d converter control register 2 22 h (r/w) adcd a/d converter data register 23 h vacancy 24 h (r/w) eic1 external interrupt 1 control register 1 25 h (r/w) eic2 external interrupt 1 control register 2 26 h to 7b h vacancy 7c h (w) ilr1 interrupt level setting register 1 7d h (w) ilr2 interrupt level setting register 2 7e h (w) ilr3 interrupt level setting register 3 7f h vacancy
30 mb89620r series n electrical characteristics 1. absolute maximum ratings (av ss = v ss = 0.0 v) *1: use av cc and v cc set to the same voltage. take care so that av cc does not exceed v cc , such as when power is turned on. *2: v i and v o must not exceed v cc + 0.3 v. warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. parameter symbol value unit remarks min. max. power supply voltage v cc av cc v ss ?0.3 v ss + 7.0 v * 1 a/d converter reference input voltage avr v ss ?0.3 v ss + 7.0 v avr must not exceed av cc + 0.3 v. input voltage v i v ss ?0.3 v cc + 0.3 v except p40 to p47* 2 v i2 v ss ?0.3 v ss + 7.0 v p40 to p47 output voltage v o v ss ?0.3 v cc + 0.3 v except p40 to p47* 2 v o2 v ss ?0.3 v ss + 7.0 v p40 to p47 ? level maximum output current i ol ? 20 ma ? level average output current i olav ? 4ma average value (operating current operating rate) ? level total maximum output current ? i ol ? 100 ma ? level total average output current ? i olav ? 40 ma average value (operating current operating rate) ? level maximum output current i oh ? ?0 ma ? level average output current i ohav ? ? ma average value (operating current operating rate) ? level total maximum output current ? i oh ? ?0 ma ? level total average output current ? i ohav ? ?0 ma average value (operating current operating rate) power consumption p d ? 300 mw operating temperature t a ?0 +85 c storage temperature tstg ?5 +150 c
31 mb89620r series 2. recommended operating conditions (av ss = v ss = 0.0 v) *: these values vary with the operating frequency and analog assurance range. see figure 1 and ?. a/d converter electrical characteristics. figure 1 indicates the operating frequency of the external oscillator at an instruction cycle of 4/f c . warning: recommended operating conditions are normal operating ranges for the semiconductor device. all the devices electrical characteristics are warranted when operated within these ranges. always use semiconductor devices within the recommended operating conditions. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representative beforehand. parameter symbol value unit remarks min. max. power supply voltage v cc av cc 2.2* 6.0* v normal operation assurance range* (mb89623r/625r/626r/627r) 2.7* 6.0* v normal operation assurance range* (mb89p625/w625/p627/t627r/ w627/pv620) 1.5 6.0 v retains the ram state in stop mode a/d converter reference input voltage avr 0.0 av cc v operating temperature t a ?0 +85 c 1 2 3 4 5 6 1.0 10.0 operation assurance range 5.0 clock operating frequency (mhz) the shaded area is assured only for the mb89623r/625r/626r/627r. 2.0 3.0 4.0 6.0 7.0 8.0 9.0 analog accuracy assured in the av cc = v cc = 3.5 v to 6.0 v range operating voltage (v) note: figure 1 operating voltage vs. clock operating frequency
32 mb89620r series 3. dc characteristics (av cc = v cc = 5.0 v, av ss = v ss = 0.0 v, t a = ?0 c to +85 c) (continued) parameter symbol pin name condition value unit remarks min. typ. max. ? level input voltage v ih p00 to p07, p10 to p17, p22, p23 ? 0.7 v cc ? v cc + 0.3 v v ihs rst , mod0, mod1, p30 to p37, p60 to p64 ? 0.8 v cc ? v cc + 0.3 v v ihs2 p40 to p47 ? 0.8 v cc ? v cc + 0.3 v ? level input voltage v il p00 to p07, p10 to p17, p22, p23 ? v ss - 0.3 ? 0.3 v cc v v ils rst , mod0, mod1, p30 to p37, p40 to p47, p60 to p64 ? v ss - 0.3 ? 0.2 v cc v open-drain output pin application voltage v d ? v ss - 0.3 ? v cc + 0.3 v v d2 ? v ss - 0.3 ? v ss + 6.0 v ? level output voltage v oh p00 to p07, p10 to p17, p20 to p27, p30 to p37 i oh = ?.0 ma 4.0 ?? v ? level output voltage v ol p00 to p07, p10 to p17, p20 to p27, p30 to p37, p40 to p47, p50 to p57 i ol = +4.0 ma ?? 0.4 v v ol2 rst ?? 0.4 v input leakage current (hi-z output leakage current) i li1 p00 to p07, p10 to p17, p20 to p27, p30 to p37, p40 to p47, p60 to p64, mod0, mod1 0.0 v < v i < v cc ?? 5 m a without pull-up resistor pull-up resistance r pull p00 to p07, p10 to p17, p30 to p37, p40 to p47, p50 to p57, p60 to p64, rst v i = 0.0 v 25 50 100 k w p50 to p57 p40 to p47
33 mb89620r series (continued) (av cc = v cc = 5.0 v, av ss = v ss = 0.0 v, t a = ?0 c to +85 c) *1: in the case of the mb89pv620, the current consumed by the connected eprom and ice is not included. the power supply current is measured at the external clock. *2: for information on t inst , see ?4) instruction cycle in ?. ac characteristics. parameter symbol pin name condition value unit remarks min. typ. max. power supply current *1 i cc v cc f c = 10 mhz normal operating mode t inst *2 = 0.4 m s 9 15 ma mb89623r/ 625r/626r/ 627r/t627r/ pv620 ?018ma mb89p625/ w625 mb89p627/ w627 i ccs f c = 10 mhz sleep mode t inst *2 = 0.4 m s ? 4ma i cch stop mode t a = +25 c 1 m a i a av cc f c = 10 mhz, when starting a/d conversion ? 3ma i ah f c = 10 mhz, t a = +25 c, when stopping a/d conversion 1 m a input capacitance c in other than av cc , av ss , v cc , and v ss f = 1 mhz 10 ? pf
34 mb89620r series 4. ac characteristics (1) reset timing (v cc = +5.0 v 10%, av ss = v ss = 0.0 v, t a = ?0 c to +85 c) note: t xcyl is the oscillation cycle (1/f c ) to input to the x0 pin. (2) power-on reset (av ss = v ss = 0.0 v, t a = ?0 c to +85 c) note: make sure that power supply rises within the selected oscillation stabilization time. if power supply voltage needs to be varied in the course of operation, a smooth voltage rise is recommended. parameter symbol condition value unit remarks min. max. rst ? pulse width t zlzh 16 t xcyl ?s parameter symbol condition value unit remarks min. max. power supply rising time t r 50 ms power-on reset function only power supply cut-off time t off 1 ms due to repeated operations 0.2 v cc 0.2 v cc rst t zlzh 0.2 v 0.2 v 2.0 v v cc 0.2 v t r t off
35 mb89620r series (3) clock timing (av ss = v ss = 0.0 v, t a = ?0 c to +85 c) (4) instruction cycle parameter symbol pin name condition value unit remarks min. max. clock frequency f c x0, x1 1 10 mhz clock cycle time t xycl x0, x1 100 1000 ns input clock pulse width p wh p wl x0 20 ns external clock input clock rising/falling time t cr t cf x0 10 ns external clock parameter symbol value (typical) unit remarks instruction cycle (minimum execution time) t inst 4/f c m s t inst = 0.4 m s when operating at f c = 10 mhz 0.2 v cc 0.8 v cc x0 0.2 v cc t cr t cf 0.8 v cc 0.2 v cc x0 x1 x0 x1 when a crystal or ceramic resonator is used when an external clock is used open t xcyl p wl p wh x0 and x1 timing and conditions clock conditions
36 mb89620r series (5) clock output timing (v cc = +5.0 v 10%, av ss = v ss = 0.0 v, t a = ?0 c to +85 c) parameter symbol pin name condition value unit remarks min. max. cycle time t cyc clk 200 ns t xcyl 2 at 10 mhz oscillation clk - ? clk t chcl 30 100 ns approx. t cyc /2 at 10 mhz oscillation 2.4 v clk 0.8 v 2.4 v t cyc t chcl
37 mb89620r series (6) bus read timing (v cc = +5.0 v 10%, f c = 10 mhz, av ss = v ss = 0.0 v, t a = ?0 c to +85 c) *: for information on t inst , see ?4) instruction cycle.? parameter symbol pin name condition value unit remarks min. max. valid address ? rd time t avrl rd , a15 to a08, ad7 to ad0 1/4 t inst *?64 ns m s rd pulse width t rlrh rd 1/4 t inst *?20 ns m s valid address ? data read time t avdv ad7 to ad0, a15 to a08 1/2 t inst * m s in the case of no wait rd ? data read time t rldv rd , ad7 to ad0 1/2 t inst *?80 ns m s in the case of no wait rd - ? data hold time t rhdx ad7 to ad0, rd 0 m s rd - ? ale - time t rhlh rd , ale 1/4 t inst *?40 ns m s rd - ? address invalid time t rhax rd , a15 to a08 1/4 t inst *?40 ns m s rd ? clk - time t rlch rd , clk 1/4 t inst *?40 ns m s clk ? rd - time t clrh 0ns rd ? bufc time t rlbl rd , bufc ? m s bufc - ? valid address time t bhav a15 to a08, ad7 to ad0, bufc 5 m s ale ad a rd bufc clk 2.4 v 0.8 v 0.8 v 2.4 v 0.8 v 0.7 v cc 0.3 v cc 0.7 v cc 0.3 v cc 2.4 v 0.8 v 2.4 v 0.8 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 2.4 v 0.8 v t rhdx t bhav t rlbl t clrh t rhlh t avdv t avrl t rlch t rlrh t rhax t rldv
38 mb89620r series (7) bus write timing (v cc = +5.0 v 10%, f c = 10 mhz, av ss = v ss = 0.0 v, t a = ?0 c to +85 c) *1: for information on t inst , see ?4) instruction cycle. *2: these characteristics are also applicable to the bus read timing. parameter symbol pin name condition value unit remarks min. max. valid address ? ale time t avll ad7 to ad0, ale, a15 to a08 1/4 t inst * 1 ?64 ns m s ale time ? address invalid time t llax ad7 to ad0, ale, a15 to a08 5ns valid address ? wr time t avwl wr , ale 1/4 t inst * 1 ?60 ns m s wr pulse width t wlwh wr 1/2 t inst * 1 ?20 ns m s write data ? wr - time t dvwh ad7 to ad0, wr 1/2 t inst * 1 ?60 ns m s wr - ? address invalid time t whax wr , a15 to a08 1/4 t inst * 1 ?40 ns ?s wr - ? data hold time t whdx ad7 to ad0, wr 1/4 t inst * 1 ?40 ns m s wr - ? ale - time t whlh wr , ale 1/4 t inst * 1 ?40 ns m s wr ? clk - time t wlch wr , clk 1/4 t inst * 1 ?40 ns m s clk ? wr - time t clwh 0ns ale pulse width t lhll ale 1/4 t inst * 1 ?35 ns* 2 m s ale ? clk - time t llch ale,clk 1/4 t inst * 1 ?30 ns* 2 m s ale ad a wr clk 2.4 v 0.8 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v t clwh 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v t llax t lhll t llch t whlh t avll t dvwh t whdx t wlch t whax t avwl t wlwh
39 mb89620r series (8) ready input timing (v cc = +5.0 v 10%, f c = 10 mhz, av ss = v ss = 0.0 v, t a = ?0 c to +85 c) *: these characteristics are also applicable to the read cycle. parameter symbol pin name condition value unit remarks min. max. rdy valid ? clk - time t yvch rdy, clk 60 ns * clk - ? rdy invalid time t chyx 0 ns * clk ale ad a wr rdy address t yvch t chyx t yvch t chyx 2.4 v 2.4 v note: the bus cycle is also extended in the read cycle in the same manner. data
40 mb89620r series (9) serial i/o timing (v cc = +5.0 v 10%, av ss = v ss = 0.0 v, t a = ?0 c to +85 c) *: for information on t inst , see ?4) instruction cycle. parameter symbol pin name condition value unit remarks min. max. serial clock cycle time t scyc sck1, sck2 internal shift clock mode 2 t inst * m s sck1 ? so1 time sck2 ? so2 time t slov sck1, so1 sck2, so2 ?00 200 ns valid si1 ? sck1 - valid si2 ? sck2 - t ivsh si1, sck1 si2, sck2 1/2 t inst * m s sck1 - ? valid si1 hold time sck2 - ? valid si2 hold time t shix sck1, si1 sck2, si2 1/2 t inst * m s serial clock ? pulse width t shsl sck1, sck2 external shift clock mode 1 t inst * m s serial clock ? pulse width t slsh sck1, sck2 1 t inst * m s sck1 ? so1 time sck2 ? so2 time t slov sck1, so1 sck2, so2 0 200 ns valid si1 ? sck1 - valid si2 ? sck2 - t ivsh si1, sck1 si2, sck2 1/2 t inst * m s sck1 - ? valid si1 hold time sck2 - ? valid si2 hold time t shix sck1, si1 sck2, si2 1/2 t inst * m s
41 mb89620r series internal shift clock mode external shift clock mode 0.8 v 2.4 v t scyc 2.4 v t slov 0.2 v cc t shix 0.8 v 0.8 v t ivsh 0.8 v cc 0.2 v cc 0.8 v cc sck1 sck2 so1 so2 si1 si2 t slsh 2.4 v t slov 0.2 v cc t shix 0.8 v cc 0.8 v t ivsh 0.8 v cc 0.2 v cc 0.8 v cc sck1 sck2 so1 so2 si1 si2 t shsl 0.8 v cc 0.2 v cc 0.2 v cc
42 mb89620r series (10) peripheral input timing (v cc = +5.0 v 10%, av ss = v ss = 0.0 v, t a = ?0 c to +85 c) *: for information on t inst, see ?4) instruction cycle. parameter symbol pin name condition value unit remarks min. max. peripheral input ? pulse width 1 t ilih1 pwc, ec, int0 to int3 2 t inst * m s peripheral input ? pulse width 1 t ihil1 2 t inst * m s peripheral input ? pulse width 2 t ilih2 adst a/d mode 32 t inst * m s peripheral input ? pulse width 2 t ihil2 32 t inst * m s peripheral input ? pulse width 2 t ilih2 sense mode 8 t inst * m s peripheral input ? pulse width 2 t ihil2 8 t inst * m s 0.2 v cc 0.8 v cc t ihil1 0.8 v cc pwc ec int0 to int3 0.2 v cc t ilih1 0.2 v cc 0.8 v cc t ihil2 0.8 v cc adst 0.2 v cc t ilih2
43 mb89620r series 5. a/d converter electrical characteristics (av cc = v cc = +3.5 v to +6.0 v, av ss = v ss = 0.0 v, t a = ?0 c to +85 c) *: for information on t inst , see ?4) instruction cycle?in ? ac characteristics. 6. a/d converter glossary resolution analog changes that are identi?ble with the a/d converter. when the number of bits is 8, analog voltage can be divided into 2 8 = 256. linearity error (unit: lsb) the deviation of the straight line connecting the zero transition point (?000 0000 ? ?000 0001? with the full-scale transition point (?111 1111 ? ?111 1110? from actual conversion characteristics differential linearity error (unit: lsb) the deviation of input voltage needed to change the output code by 1 lsb from the theoretical value total error (unit: lsb) the difference between theoretical and actual conversion values parameter symbol pin name condition value unit remarks min. typ. max. resolution 8 bit total error avr = av cc 1.5 lsb linearity error 1.0 lsb differential linearity error 0.9 lsb zero transition voltage v ot av ss ?1.0 lsb av ss + 0.5 lsb av ss + 2.0 lsb mv full-scale transition voltage v fst avr ?3.0 lsb avr ?1.5 lsb avr mv interchannel disparity 0.5 lsb a/d mode conversion time 44 t inst * m s sense mode conversion time 12 t inst * m s analog port input current i ain an0 to an7 10 m a analog input voltage 0.0 avr v reference voltage avr 0.0 av cc v reference voltage supply current i r avr = 5.0 v, when starting a/d conversion 100 ?m a i rh avr = 5.0 v, when stopping a/d conversion 1 m a
44 mb89620r series 7. notes on using a/d converter input impedance of the analog input pins the a/d converter contains a sample hold circuit as illustrated below to fetch analog input voltage into the sample hold capacitor for eight instruction cycles after activating a/d conversion. for this reason, if the output impedance of the external circuit for the analog input is high, analog input voltage might not stabilize within the analog input sampling period. therefore, it is recommended to keep the output impedance of the external circuit low (below 10 k w ). note that if the impedance cannot be kept low, it is recommended to connect an external capacitor of about 0.1 m f for the analog input pin. error the smaller the | avr ?av ss |, the greater the error would become relatively. v ot v nt v (n + i)t v fst digital output (1 lsb n + v ot ) 0000 0000 0000 0000 0001 0010 1111 1111 1110 1111 1 lsb = avr 256 linearity error = v nt ?(1 lsb n + v ot ) 1 lsb analog input differential linearity error = v ( n + 1 ) t ? nt 1 lsb ? total error = 1 lsb v nt ?(1 lsb n + 1 lsb) linearity error theoretical conversion value actual conversion value v ot v nt v (n + i)t v fst digital output (1 lsb n + v ot ) 0000 0000 0000 0000 0001 0010 1111 1111 1110 1111 1 lsb = avr 256 linearity error = v nt ?(1 lsb n + v ot ) 1 lsb analog input differential linearity error = v ( n + 1 ) t ? nt 1 lsb ? total error = 1 lsb v nt ?(1 lsb n + 1 lsb) linearity error theoretical conversion value actual conversion value analog channel selector analog input pin comparator close for 8 instruction cycles after activating a/d conversion. if the analog input impedance is higher than 10 k w , it is recommended to connect an external capacitor of approx. 0.1 m f. r = 6 k w . . sample hold circuit c = 33 pf . . analog input equivalent circiut analog channel selector analog input pin comparator close for 8 instruction cycles after activating a/d conversion. if the analog input impedance is higher than 10 k w , it is recommended to connect an external capacitor of approx. 0.1 m f. r = 6 k w . . sample hold circuit c = 33 pf . . analog channel selector analog input pin comparator close for 8 instruction cycles after activating a/d conversion. if the analog input impedance is higher than 10 k w , it is recommended to connect an external capacitor of approx. 0.1 m f. r = 6 k w . . sample hold circuit c = 33 pf . .
45 mb89620r series n example characteristics 012 3 456 7 v cc (v) 5.0 v in (v) v in vs. v cc 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 t a = +25 c 012 3 456 7 v cc (v) 5.0 v in (v) v in vs. v cc 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 v ihs v ils t a = +25 c 0.0 1.0 v cc ?v oh (v) v cc = 2.5 v v cc = 3.0 v v cc = 4.0 v v cc = 5.0 v v cc = 6.0 v i oh (ma) v cc v oh vs. i oh 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 ?.5 ?.0 ?.5 ?.0 ?.5 ?.0 t a = +25 c 010 123456789 0.1 0.2 0.3 0.4 0.5 v ol (v) v cc = 3.0 v v cc = 4.0 v v cc = 5.0 v v cc = 6.0 v i ol (ma) v ol vs. i ol t a = +25 c (1) ? level output voltage (2) ? level output voltage (3) ? level input voltage/? level input (4) ? level input voltage/? level input voltage (cmos input) voltage (hysteresis input) v ihs : threshold when input voltage in hysteresis v ils : threshold when input voltage in hysteresis characteristics is set to ? level characteristics is set to ? level
46 mb89620r series r pull vs. v cc 234 5 6 r pull (k w ) 10 1 100 1000 t a = +25 c v cc (v) i a (ma) av cc (v) 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 t a = +25 c f c = 10 mhz i a vs. av cc i r ( m a) avr (v) 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 20 40 60 80 100 120 140 160 180 200 t a = +25 c i r vs. a vr (5) power supply current (external clock) (6) pull-up resistance i cc (ma) 3456 v cc (v) 0 2 4 6 i cc vs. v cc t a = +25 c 7 2 1 8 10 12 14 16 f c = 10 mhz f c = 8 mhz f c = 4 mhz f c = 1 mhz i ccs (ma) 3456 v cc (v) 0 2 3 4 i ccs vs. v cc t a = +25 c 7 2 1 5 f c = 10 mhz f c = 8 mhz f c = 4 mhz f c = 1 mhz 1
47 mb89620r series n instructions execution instructions can be divided into the following four groups: transfer arithmetic operation branch others table 1 lists symbols used for notation of instructions. table 1 instruction symbols (continued) symbol meaning dir direct address (8 bits) off offset (8 bits) ext extended address (16 bits) #vct vector table number (3 bits) #d8 immediate data (8 bits) #d16 immediate data (16 bits) dir: b bit direct address (8:3 bits) rel branch relative address (8 bits) @ register indirect (example: @a, @ix, @ep) a accumulator a (whether its length is 8 or 16 bits is determined by the instruction in use.) ah upper 8 bits of accumulator a (8 bits) al lower 8 bits of accumulator a (8 bits) t temporary accumulator t (whether its length is 8 or 16 bits is determined by the instruction in use.) th upper 8 bits of temporary accumulator t (8 bits) tl lower 8 bits of temporary accumulator t (8 bits) ix index register ix (16 bits)
48 mb89620r series (continued) columns indicate the following: mnemonic: assembler notation of an instruction ~: number of instructions #: number of bytes operation: operation of an instruction tl, th, ah: a content change when each of the tl, th, and ah instructions is executed. symbols in the column indicate the following: ? indicates no change. dh is the 8 upper bits of operation description data. al and ah must become the contents of al and ah immediately before the instruction is executed. 00 becomes 00. n, z, v, c: an instruction of which the corresponding ?g will change. if + is written in this column, the relevant instruction will change its corresponding ?g. op code: code of an instruction. if an instruction is more than one code, it is written according to the following rule: example: 48 to 4f ? this indicates 48, 49, ... 4f. symbol meaning ep extra pointer ep (16 bits) pc program counter pc (16 bits) sp stack pointer sp (16 bits) ps program status ps (16 bits) dr accumulator a or index register ix (16 bits) ccr condition code register ccr (8 bits) rp register bank pointer rp (5 bits) ri general-purpose register ri (8 bits, i = 0 to 7) indicates that the very is the immediate data. (whether its length is 8 or 16 bits is determined by the instruction in use.) ( ) indicates that the contents of is the target of accessing. (whether its length is 8 or 16 bits is determined by the instruction in use.) (( )) the address indicated by the contents of is the target of accessing. (whether its length is 8 or 16 bits is determined by the instruction in use.)
49 mb89620r series table 2 transfer instructions (48 instructions) notes: during byte transfer to a, t ? a is restricted to low bytes. operands in more than one operand instruction must be stored in the order in which their mnemonics are written. (reverse arrangement of f 2 mc-8 family) mnemonic ~ # operation tl th ah n z v c op code mov dir,a mov @ix +off,a mov ext,a mov @ep,a mov ri,a mov a,#d8 mov a,dir mov a,@ix +off mov a,ext mov a,@a mov a,@ep mov a,ri mov dir,#d8 mov @ix +off,#d8 mov @ep,#d8 mov ri,#d8 movw dir,a movw @ix +off,a movw ext,a movw @ep,a movw ep,a movw a,#d16 movw a,dir movw a,@ix +off movw a,ext movw a,@a movw a,@ep movw a,ep movw ep,#d16 movw ix,a movw a,ix movw sp,a movw a,sp mov @a,t movw @a,t movw ix,#d16 movw a,ps movw ps,a movw sp,#d16 swap setb dir: b clrb dir: b xch a,t xchw a,t xchw a,ep xchw a,ix xchw a,sp movw a,pc 3 4 4 3 3 2 3 4 4 3 3 3 4 5 4 4 4 5 5 4 2 3 4 5 5 4 4 2 3 2 2 2 2 3 4 3 2 2 3 2 4 4 2 3 3 3 3 2 2 2 3 1 1 2 2 2 3 1 1 1 3 3 2 2 2 2 3 1 1 3 2 2 3 1 1 1 3 1 1 1 1 1 1 3 1 1 3 1 2 2 1 1 1 1 1 1 (dir) ? (a) ( (ix) +off ) ? (a) (ext) ? (a) ( (ep) ) ? (a) (ri) ? (a) (a) ? d8 (a) ? (dir) (a) ? ( (ix) +off) (a) ? (ext) (a) ? ( (a) ) (a) ? ( (ep) ) (a) ? (ri) (dir) ? d8 ( (ix) +off ) ? d8 ( (ep) ) ? d8 (ri) ? d8 (dir) ? (ah),(dir + 1) ? (al) ( (ix) +off) ? (ah), ( (ix) +off + 1) ? (al) (ext) ? (ah), (ext + 1) ? (al) ( (ep) ) ? (ah),( (ep) + 1) ? (al) (ep) ? (a) (a) ? d16 (ah) ? (dir), (al) ? (dir + 1) (ah) ? ( (ix) +off), (al) ? ( (ix) +off + 1) (ah) ? (ext), (al) ? (ext + 1) (ah) ? ( (a) ), (al) ? ( (a) ) + 1) (ah) ? ( (ep) ), (al) ? ( (ep) + 1) (a) ? (ep) (ep) ? d16 (ix) ? (a) (a) ? (ix) (sp) ? (a) (a) ? (sp) ( (a) ) ? (t) ( (a) ) ? (th),( (a) + 1) ? (tl) (ix) ? d16 (a) ? (ps) (ps) ? (a) (sp) ? d16 (ah) ? (al) (dir): b ? 1 (dir): b ? 0 (al) ? (tl) (a) ? (t) (a) ? (ep) (a) ? (ix) (a) ? (sp) (a) ? (pc) al al al al al al al al al al al al al al al ah ah ah ah ah ah ah dh dh dh dh dh dh dh dh dh dh al dh dh dh dh dh ??? ??? ??? ??? ??? + + ? + + ? + + ? + + ? + + ? + + ? + + ? ??? ??? ??? ??? ??? ??? ??? ??? ??? + + ? + + ? + + ? + + ? + + ? + + ? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? + + + + ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? 45 46 61 47 48 to 4f 04 05 06 60 92 07 08 to 0f 85 86 87 88 to 8f d5 d6 d4 d7 e3 e4 c5 c6 c4 93 c7 f3 e7 e2 f2 e1 f1 82 83 e6 70 71 e5 10 a8 to af a0 to a7 42 43 f7 f6 f5 f0
50 mb89620r series table 3 arithmetic operation instructions (62 instructions) (continued) mnemonic ~ # operation tl th ah n z v c op code addc a,ri addc a,#d8 addc a,dir addc a,@ix +off addc a,@ep addcw a addc a subc a,ri subc a,#d8 subc a,dir subc a,@ix +off subc a,@ep subcw a subc a inc ri incw ep incw ix incw a dec ri decw ep decw ix decw a mulu a divu a andw a orw a xorw a cmp a cmpw a rorc a rolc a cmp a,#d8 cmp a,dir cmp a,@ep cmp a,@ix +off cmp a,ri daa das xor a xor a,#d8 xor a,dir xor a,@ep xor a,@ix +off xor a,ri and a and a,#d8 and a,dir 3 2 3 4 3 3 2 3 2 3 4 3 3 2 4 3 3 3 4 3 3 3 19 21 3 3 3 2 3 2 2 2 3 3 4 3 2 2 2 2 3 3 4 3 2 2 3 1 2 2 2 1 1 1 1 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 2 1 1 1 1 2 2 1 2 1 1 2 2 (a) ? (a) + (ri) + c (a) ? (a) + d8 + c (a) ? (a) + (dir) + c (a) ? (a) + ( (ix) +off) + c (a) ? (a) + ( (ep) ) + c (a) ? (a) + (t) + c (al) ? (al) + (tl) + c (a) ? (a) - (ri) - c (a) ? (a) - d8 - c (a) ? (a) - (dir) - c (a) ? (a) - ( (ix) +off) - c (a) ? (a) - ( (ep) ) - c (a) ? (t) - (a) - c (al) ? (tl) - (al) - c (ri) ? (ri) + 1 (ep) ? (ep) + 1 (ix) ? (ix) + 1 (a) ? (a) + 1 (ri) ? (ri) - 1 (ep) ? (ep) - 1 (ix) ? (ix) - 1 (a) ? (a) - 1 (a) ? (al) (tl) (a) ? (t) / (al),mod ? (t) (a) ? (a) (t) (a) ? (a) (t) (a) ? (a) " (t) (tl) - (al) (t) - (a) (a) - d8 (a) - (dir) (a) - ( (ep) ) (a) - ( (ix) +off) (a) - (ri) decimal adjust for addition decimal adjust for subtraction (a) ? (al) " (tl) (a) ? (al) " d8 (a) ? (al) " (dir) (a) ? (al) " ( (ep) ) (a) ? (al) " ( (ix) +off) (a) ? (al) " (ri) (a) ? (al) (tl) (a) ? (al) d8 (a) ? (al) (dir) dl 00 dh dh dh dh dh 00 dh dh dh + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ??? ??? + + ? + + + ??? ??? + + ? ??? ??? + + r + + r + + r + + + + + + + + + + ?+ + + ?+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + r + + r + + r + + r + + r + + r + + r + + r + + r 28 to 2f 24 25 26 27 23 22 38 to 3f 34 35 36 37 33 32 c8 to cf c3 c2 c0 d8 to df d3 d2 d0 01 11 63 73 53 12 13 03 02 14 15 17 16 18 to 1f 84 94 52 54 55 57 56 58 to 5f 62 64 65 a c ? ? ?? a c
51 mb89620r series (continued) table 4 branch instructions (17 instructions) table 5 other instructions (9 instructions) mnemonic ~ # operation tl th ah n z v c op code and a,@ep and a,@ix +off and a,ri or a or a,#d8 or a,dir or a,@ep or a,@ix +off or a,ri cmp dir,#d8 cmp @ep,#d8 cmp @ix +off,#d8 cmp ri,#d8 incw sp decw sp 3 4 3 2 2 3 3 4 3 5 4 5 4 3 3 1 2 1 1 2 2 1 2 1 3 2 3 2 1 1 (a) ? (al) ( (ep) ) (a) ? (al) ( (ix) +off) (a) ? (al) (ri) (a) ? (al) (tl) (a) ? (al) d8 (a) ? (al) (dir) (a) ? (al) ( (ep) ) (a) ? (al) ( (ix) +off) (a) ? (al) (ri) (dir) ?d8 ( (ep) ) ?d8 ( (ix) + off) ?d8 (ri) ?d8 (sp) ? (sp) + 1 (sp) ? (sp) ?1 + + r + + r + + r + + r + + r + + r + + r + + r + + r + + + + + + + + + + + + + + + + ??? ??? 67 66 68 to 6f 72 74 75 77 76 78 to 7f 95 97 96 98 to 9f c1 d1 mnemonic ~ # operation tl th ah n z v c op code bz/beq rel bnz/bne rel bc/blo rel bnc/bhs rel bn rel bp rel blt rel bge rel bbc dir: b,rel bbs dir: b,rel jmp @a jmp ext callv #vct call ext xchw a,pc ret reti 3 3 3 3 3 3 3 3 5 5 2 3 6 6 3 4 6 2 2 2 2 2 2 2 2 3 3 1 3 1 3 1 1 1 if z = 1 then pc ? pc + rel if z = 0 then pc ? pc + rel if c = 1 then pc ? pc + rel if c = 0 then pc ? pc + rel if n = 1 then pc ? pc + rel if n = 0 then pc ? pc + rel if v " n = 1 then pc ? pc + rel if v " n = 0 then pc ? pc + rei if (dir: b) = 0 then pc ? pc + rel if (dir: b) = 1 then pc ? pc + rel (pc) ? (a) (pc) ? ext vector call subroutine call (pc) ? (a),(a) ? (pc) + 1 return from subrountine return form interrupt dh ??? ??? ??? ??? ??? ??? ??? ??? ?+ ? ?+ ? ??? ??? ??? ??? ??? ??? restore fd fc f9 f8 fb fa ff fe b0 to b7 b8 to bf e0 21 e8 to ef 31 f4 20 30 mnemonic ~ # operation tl th ah n z v c op code pushw a popw a pushw ix popw ix nop clrc setc clri seti 4 4 4 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 dh ??? ??? ??? ??? ??? ???r ???s ??? ??? 40 50 41 51 00 81 91 80 90
52 mb89620r series n instruction map l h 0123456789abcdef 0 nop swap ret reti pushw a popw a mov a,ext movw a,ps clri seti clrb dir: 0 bbc dir: 0,rel incw a decw a jmp @a movw a,pc 1 mulu a divu a jmp addr16 call addr16 pushw ix popw ix mov ext,a movw ps,a clrc setc clrb dir: 1 bbc dir: 1,rel incw sp decw sp movw sp,a movw a,sp 2 rolc a cmp a addc a subc a xch a, t xor a and a or a mov @a,t mov a,@a clrb dir: 2 bbc dir: 2,rel incw ix decw ix movw ix,a movw a,ix 3 rorc a cmpw a addcw a subcw a xchw a, t xorw a andw a orw a movw @a,t movw a,@a clrb dir: 3 bbc dir: 3,rel incw ep decw ep movw ep,a movw a,ep 4 mov a,#d8 cmp a,#d8 addc a,#d8 subc a,#d8 xor a,#d8 and a,#d8 or a,#d8 daa das clrb dir: 4 bbc dir: 4,rel movw a,ext movw ext,a movw a,#d16 xchw a,pc 5 mov a,dir cmp a,dir addc a,dir subc a,dir mov dir,a xor a,dir and a,dir or a,dir mov dir,#d8 cmp dir,#d8 clrb dir: 5 bbc dir: 5,rel movw a,dir movw dir,a movw sp,#d16 xchw a,sp 6 mov a,@ix +d cmp a,@ix +d addc a,@ix +d subc a,@ix +d mov @ix +d,a xor a,@ix +d and a,@ix +d or a,@ix +d mov @ix +d,#d8 cmp @ix +d,#d8 clrb dir: 6 bbc dir: 6,rel movw a,@ix +d movw @ix +d,a movw ix,#d16 xchw a,ix 7 mov a,@ep cmp a,@ep addc a,@ep subc a,@ep mov @ep,a xor a,@ep and a,@ep or a,@ep mov @ep,#d8 cmp @ep,#d8 clrb dir: 7 bbc dir: 7,rel movw a,@ep movw @ep,a movw ep,#d16 xchw a,ep 8 mov a,r0 cmp a,r0 addc a,r0 subc a,r0 mov r0,a xor a,r0 and a,r0 or a,r0 mov r0,#d8 cmp r0,#d8 setb dir: 0 bbs dir: 0,rel inc r0 dec r0 callv #0 bnc rel 9 mov a,r1 cmp a,r1 addc a,r1 subc a,r1 mov r1,a xor a,r1 and a,r1 or a,r1 mov r1,#d8 cmp r1,#d8 setb dir: 1 bbs dir: 1,rel inc r1 dec r1 callv #1 bc rel a mov a,r2 cmp a,r2 addc a,r2 subc a,r2 mov r2,a xor a,r2 and a,r2 or a,r2 mov r2,#d8 cmp r2,#d8 setb dir: 2 bbs dir: 2,rel inc r2 dec r2 callv #2 bp rel b mov a,r3 cmp a,r3 addc a,r3 subc a,r3 mov r3,a xor a,r3 and a,r3 or a,r3 mov r3,#d8 cmp r3,#d8 setb dir: 3 bbs dir: 3,rel inc r3 dec r3 callv #3 bn rel c mov a,r4 cmp a,r4 addc a,r4 subc a,r4 mov r4,a xor a,r4 and a,r4 or a,r4 mov r4,#d8 cmp r4,#d8 setb dir: 4 bbs dir: 4,rel inc r4 dec r4 callv #4 bnz rel d mov a,r5 cmp a,r5 addc a,r5 subc a,r5 mov r5,a xor a,r5 and a,r5 or a,r5 mov r5,#d8 cmp r5,#d8 setb dir: 5 bbs dir: 5,rel inc r5 dec r5 callv #5 bz rel e mov a,r6 cmp a,r6 addc a,r6 subc a,r6 mov r6,a xor a,r6 and a,r6 or a,r6 mov r6,#d8 cmp r6,#d8 setb dir: 6 bbs dir: 6,rel inc r6 dec r6 callv #6 bge rel f mov a,r7 cmp a,r7 addc a,r7 subc a,r7 mov r7,a xor a,r7 and a,r7 or a,r7 mov r7,#d8 cmp r7,#d8 setb dir: 7 bbs dir: 7,rel inc r7 dec r7 callv #7 blt rel
53 mb89620r series n mask options note: reset is input asynchronized with the internal clock whether with or without power-on reset. no. part number mb89623r mb89625r mb89626r mb89627r mb89p625 mb89w625 mb89p627 mb89w627 mb89pv620 mb89t627r specifying procedure specify when ordering masking set with eprom programmer setting not possible 1 pull-up resistors p00 to p07, p10 to p17, p30 to p37, p40 to p47, p50 to p57, p60 to p64 selectable per pin. (p50 to p57 must be set to without a pull-up resistor when an a/d converter is used.) can be set per pin. (p40 to p47 are available only for without a pull-up resistor.) fixed to without pull-up resistor 2 power-on reset selection with power-on reset without power-on reset selectable setting possible fixed to with power-on reset 3 oscillation stabilization time selection crystal oscillator: 2 18 /f c (s)) ceramic oscillator: 2 14 /f c (s)) selectable setting possible crystal oscillator (2 18 /f c (s)) 4 reset pin output with reset output without reset output selectable setting possible with reset output
54 mb89620r series n ordering information part number package remarks mb89623rp-sh mb89625rp-sh mb89626rp-sh mb89627rp-sh mb89p625p-sh mb89p627-sh mb89t627rp-sh 64-pin plastic sh-dip (dip-64p-m01) mb89623rpfv mb89625rpfv 64-pin plastic lqfp (fpt-64p-m03) lead pitch: 0.5 mm mb89623rpf mb89625rpf mb89626rpf mb89627rpf mb89p625pf mb89p627pf mb89t623rpf mb89t625rpf mb89t627rpf 64-pin plastic qfp (fpt-64p-m06) lead pitch: 1.0 mm mb89623rpfm mb89625rpfm mb89626rpfm mb89627rpfm mb89p625pfm mb89t627rpfm 64-pin plastic qfp (fpt-64p-m09) lead pitch: 0.65 mm mb89w625c-sh mb89w627c-sh 64-pin ceramic sh-dip (dip-64c-a06) mb89pv620cf 64-pin ceramic mqfp (mqp-64c-p01) mb89pv620c-sh 64-pin ceramic mdip (mdp-64c-p02)
55 mb89620r series n package dimensions +0.50 C0 C0 +.020 C.022 +.008 C0.55 +0.22 55.118(2.170)ref index-2 15max typ 19.05(.750) (.010.002) 0.250.05 max 1.778(.070) (.070.007) 1.7780.18 1.00 .039 (.018.004) 0.450.10 0.51(.020)min 3.00(.118)min 5.65(.222)max index-1 (.669.010) 17.000.25 2.283 58.00 1994 fujitsu limited d64001s-3c-4 c dimensions in mm (inches) 64-pin plastic sh-dip (dip-64p-m01)
56 mb89620r series c 1995 fujitsu limited f64009s-2c-5 0.10(.004) .005 ?.001 +.002 ?0.02 +0.05 0.127 .059 ?.004 +.008 ?0.10 +0.20 1.50 "a" 0.500.20 (.020.008) details of "a" part 0 10? 33 32 17 16 1 64 49 48 index lead no. (stand off) 12.000.20(.472.008)sq 10.000.10(.394.004)sq 0.500.08 (.0197.0031) .007 ?.001 +.003 ?0.03 +0.08 0.18 11.00 7.50 (.295) ref (.433) nom 0.100.10 (.004.004) dimensions in mm (inches) (mounting height) 64-pin plastic lqfp (fpt-64p-m03)
57 mb89620r series "a" lead no. 64 52 32 0.25(.010) 0.30(.012) 51 33 1 19 20 index typ (.016.004) 0.400.10 1.00(.0394) 0.150.05(.006.002) 18.00(.709)ref 22.300.40(.878.016) (stand off) 0.05(.002)min 3.35(.132)max (.551.008) 14.000.20 (.642.016) 16.300.40 ref 12.00(.472) (.736.016) 18.700.40 20.000.20(.787.008) 24.700.40(.972.016) (.047.008) details of "b" part 1.200.20 0 10 details of "a" part 0.18(.007)max 0.63(.025)max 0.10(.004) "b" m 0.20(.008) 1994 fujitsu limited f64013s-3c-2 c dimensions in mm (inches) 64-pin plastic qfp (fpt-64p-m06)
58 mb89620r series +0.20 C0.10 +.008 C.004 +0.05 C0.02 +.002 C.001 lead no. (stand off) 64 49 48 33 32 17 16 1 nom (.512) ref (.384) 13.00 9.75 (.012.004) 0.300.10 0.65(.0256)typ 12.000.10(.472.004)sq 14.000.20(.551.008)sq (.020.008) (.004.004) 0.100.10 0.500.20 0 10 details of "a" part "a" 1.50 .059 0.127 .005 1 pin index 0.10(.004) m 0.13(.005) 1994 fujitsu limited f64018s-1c-2 c 64-pin plastic qfp dimensions in mm (inches) (fpt-64p-m09)
59 mb89620r series +0.13 C0.08 C.003 +.005 0~9 5.84(.230)max 8.89(.350) dia typ (.134.014) 3.400.36 55.118(2.170)ref (.738.010) 18.750.25 (2.240.022) 56.900.56 (.750.010) 19.050.25 (.010.004) 0.250.05 1.270.25 (.050.010) 1.45(.057) max 1.7780.180 (.070.007) 0.900.10 (.0355.0040) 0.46 .018 index area r1.27(.050) ref 1994 fujitsu limited d64006sc-1-2 c dimensions in mm (inches) 64-pin ceramic sh-dip (dip-64c-a06)
60 mb89620r series +0.40 C0.20 +.016 C.008 +0.40 C0.20 +.016 C.008 1.20 .047 12.00(.472)typ (.039.010) 1.000.25 typ 18.00(.709) (.039.010) 1.000.25 (.016.004) 0.400.10 1.20 .047 (.016.004) 0.400.10 max 10.82(.426) (.006.002) 0.150.05 0.50(.020)typ 11.68(.460)typ 9.48(.373)typ 7.62(.300)typ 0.30(.012)typ (.050.005) 1.270.13 (.713.008) 18.120.20 typ 14.22(.560) typ 12.02(.473) typ 10.16(.400) typ 24.70(.972) (.878.013) 22.300.33 (.050.005) 1.270.13 typ 0.30(.012) index area 18.70(.736)typ (.642.013) 16.300.33 (.613.008) 15.580.20 1994 fujitsu limited m64004sc-1-3 c dimensions in mm (inches ) 64-pin ceramic mqfp (mqp-64c-p01)
61 mb89620r series +0.13 C0.08 +.005 C.003 index area 0~9 (.750.012) 19.050.30 0.46 .018 (2.240.025) (.010.002) 0.250.05 (.050.010) 1.270.25 (.135.015) 3.430.38 55.12(2.170)ref (.035.005) 0.900.13 (.070.010) 1.7780.25 10.16(.400)max 33.02(1.300)ref (.100.010) 2.540.25 (.738.012) 18.750.30 typ 15.24(.600) 56.900.64 1994 fujitsu limited m64002sc-1-4 c dimensions in mm (inches) 64-pin ceramic mdip (mdp-64c-p02)
62 mb89620r series fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka nakahara-ku, kawasaki-shi kanagawa 211-88, japan tel: (044) 754-3763 fax: (044) 754-3329 north and south america fujitsu microelectronics, inc. semiconductor division 3545 north first street san jose, ca 95134-1804, u.s.a. tel: (408) 922-9000 fax: (408) 432-9044/9045 europe fujitsu mikroelektronik gmbh am siebenstein 6-10 63303 dreieich-buchschlag germany tel: (06103) 690-0 fax: (06103) 690-122 asia paci? fujitsu microelectronics asia pte. limited #05-08, 151 lorong chuan new tech park singapore 556741 tel: (65) 281-0770 fax: (65) 281-0220 f9703 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade control law of japan, the prior authorization by japanese government should be required for export of those products from japan.

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